Item 1.    Business

Company Overview

        MoSys, Inc., together with its subsidiaries ("MoSys," the "Company," "we," "our" or "us"), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, and intellectual property, or IP, for the high-speed networking, communications, storage and computing markets. Our technology delivers time-to-market, performance, power and economic benefits for system original equipment manufacturers, or OEMs, and technology licensees. We have developed a family of ICs, called Bandwidth Engine, which combines our proprietary 1T-SRAM high-density embedded memory and high-speed 10 Gigabits per second, or Gbps, serial interface, or I/O, with our intelligent access technology and a highly efficient interface protocol. As the bandwidth requirements and amount of packet processing increase in high-speed networking systems, critical memory access bottlenecks occur. Our Bandwidth Engine IC with its combination of serial I/O, high-speed memory, and efficient, intelligent access drastically increases memory accesses per second, removing these bottlenecks. The first applications for our Bandwidth Engine IC are in networking and communications systems to enable next generation, high density 10 Gbps, 40 Gbps and 100 Gbps solutions. Historically, our primary business has been the design, development, marketing, sale and support of differentiated IP including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. We plan to focus on differentiated IP-rich IC products, such as the Bandwidth Engine, and are dedicating an increasing amount of our R&D, marketing and sales budget to these products.

        Since the beginning of 2010, we have invested an increasing amount of our research and development resources towards development of our Bandwidth Engine family of ICs. Our future success and ability to achieve and maintain profitability will be dependent on the marketing and sales of our Bandwidth Engine IC products into networking, communications and other markets requiring high bandwidth memory access. As a result, during 2011, we began placing less emphasis on IP licensing and deploying more resources towards our IC product development and marketing efforts. In December 2011, we sold a number of patents in an arrangement that provided $35 million in cash with no equity dilution to the Company. We intend to use the proceeds from this sale to partially fund our investment in our Bandwidth Engine IC product line. The transaction did not include any of the patents that cover our Bandwidth Engine IC product line, and we retained a license to the sold patents in order to execute current business with our IP technology customers and partners. However, the

3

Table of Contents

retained license limits, among other things, the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which, at one time, was a principal focus of our 1T-SRAM licensing activities. We still maintain a large patent portfolio with over 100 patents granted and more in process.

        We expect revenue from IP licensing and royalties to continue to represent the majority of our revenues in 2012. Our expectation is that our revenue will transition from primarily licensing and royalty to predominately IC product sales over the next two years. Due to the shift in our engineering and research and development focus and the decline in major consumer electronics applications utilizing customized versions of our 1T-SRAM technology, our competitiveness and the demand for our IP have declined since the beginning of 2011. As a result of our reduced licensing activities, we expect our licensing and royalty revenue to decrease in future periods. We do not expect to generate significant revenue from our Bandwidth Engine ICs until the second half of 2012, or later, and believe that IC revenues are unlikely to match or exceed revenues generated from licensing and royalties in 2011 until at least 2013, if at all.

Industry Background

        The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 3G and 4G wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, including video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone. To support this trend, the next generations of networking systems must offer new levels of packet forwarding rates and bandwidth density. This in turn necessitates new generations of packet processors and improved memory subsystems to enable system performance in support of these increased demands.

        Networking systems, such as routers and switches, contain network line cards. The type and number of semiconductors included on the line cards depend on the capacity, port type and target functionality of each card. Several types of semiconductors are included on each line card, including physical interface electronics, one or more packet processors and multiple memory chips. Packet processors are complex ICs developed using field programmable gate arrays, or FPGAs, application-specific integrated circuits, or ASICs, or network processing units, or NPUs, that perform high speed processing for functions, such as traffic shaping, metering, billing, statistics, detection and steering. Various types of memory ICs are used in order to facilitate the temporary storage of information embedded within each packet flowing through the processors. After a packet enters the line card through a physical interface, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the IP address, and the payload which contains the data being sent. The packet header is stripped from the packet, stored in memory ICs and processed separately by a packet processing engine on the line card. The analysis of the packet header must occur at full data rates and typically requires accessing the memory ICs multiple times. Simultaneously, the packet's payload, which may be substantially larger than the packet header, is also stored in memory ICs. The specific payload data may or may not be analyzed depending on the functionality of the line card. Once processing is complete, the packet is re-combined to be sent from the system. Within the line card, communication between the packet processor and memory ICs occurs through either a parallel or serial interface. Combinations of physical pins on each type of chip are grouped together in

4

Table of Contents

a parallel or serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next. Today, the majority of physical buses use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, in a parallel architecture the number of pins required and the speed of the bus become a limitation on system performance and capability. In a serial architecture, high speed serial bus architectures and more advanced I/O protocols will need to be supported by the various ICs included on the line card in order to remove the bottleneck and meet next generation bandwidth requirements.

        The majority of networking systems sold today include line cards that process data at speeds of 10 Gbps, but to accommodate the substantial and growing increase in demand for networking communications and applications, networking equipment companies are beginning to produce next-generation systems that run at aggregate speeds of 40 Gbps up to hundreds of Gbps. Another major challenge to system designers is what we call the "memory performance barrier." Processor performance in applications such as computing and networking have continued to nearly double every 18 months, or even faster, while the performance of memory technology has generally been able to double once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds of 10 Gbps, but will struggle to meet speeds of 40 Gbps and beyond due to system-level limitations for pin counts, power and performance. Traditional memory solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM, IC solutions. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. Substantially all of these DRAM and SRAM memory ICs use parallel interfaces, which are slower than serial interfaces and will be challenged to meet the performance requirements of networking systems greater than 40 Gbps. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which results in additional bandwidth limitation problems.

        To address the bandwidth limitations currently confronting networking system designers, we have developed our Bandwidth Engine family of ICs. We expect our Bandwidth Engine IC products to address the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our product and technology is required as a replacement of existing memory IC solutions in order to meet the needs of the next-generation networking systems that require large number of packet lookups and run at speeds greater than 40 Gbps.

Bandwidth Engine IC Product

        Our Bandwidth Engine IC combines: (1) our proprietary 1T-SRAM high-density, high-speed, low latency embedded memory, (2) our high-speed serial 10 Gbps serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM and serial I/O with logic and other functions provides a system-level solution and significantly improves overall system performance at lower cost and power consumption. Our Bandwidth Engine ICs can provide over two billion accesses per second, over twice the performance of current memory-based solutions, and enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line card level and use our

5

Table of Contents

product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may—

•

increase performance up to four times;



•

reduce power by approximately 50%;



•

reduce cost by greater than 50%; and



•

result in a dramatic reduction in IC pin counts on the line card.

        The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element.

        Our first generation Bandwidth Engine IC contains 576 megabytes, or MB, of 1T-SRAM memory and uses 10.3 Gbps SerDes I/O technology. Variations of this IC can have up to two interface ports, with up to 8 serial receiver and 8 serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an arithmetic logic unit, or ALU, that can perform read-modify-write operations. These ICs are tested to meet or exceed the standards for telecommunications carrier class and enterprise grade applications.

On-chip Functionality

        A significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs have an ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. By moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, the number of I/O transactions is reduced and the processor IC is freed up to perform other networking or micro-processing functions.

High-Performance Interface

        High speed, efficient I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking equipment system requirements necessitate an industry transition from parallel I/O to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as FPGAs and NPUs, are using serial I/Os to ensure they can match the performance of, and compete with ASICs. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical I/Os that connect an IC to the NIC) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system.

GigaChip Interface Protocol

        In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface, or GCI, which is a transport protocol optimized for efficient chip-to-chip communications. GCI is an open interface protocol, compatible with the current industry standard (Common Electrical Interface, release #11 or CEI-11). GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages

6

Table of Contents

90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and we are offering it to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

        The Bandwidth Engine uses our proprietary 1T-SRAM high density memory technology to provide the density of DRAM and the speed of SRAM. The internal multi-bank memory array architecture used in our Bandwidth Engine ICs enables concurrent access operations. We believe that this architecture is also optimized for small algorithmic operations and data transfers, such as packet header analysis.

Carrier and Enterprise Grade Quality and Reliability

        Networking equipment providers focused on the carrier and enterprise market have rigid performance and reliability standards that they require their IC vendors to achieve. Our Bandwidth Engine architecture and interface is designed for data robustness and uses end-to-end error checking and correction codes. Although the Bandwidth Engine functions as more than a discrete memory device, the onboard memory array represents a significant portion of the total chip area. Memory-dominated devices require substantially different and more robust testing than non-memory ICs in order to achieve the quality and reliability requirements of advanced networking systems. We have considered these requirements for our target customers and market segments and have incorporated appropriate design and manufacturing performance margins into our Bandwidth Engine IC products.

Our Technology

        Our historical business was focused on the licensing of our proprietary 1T-SRAM and SerDes I/O technologies. We have leveraged our proprietary IP to design our Bandwidth Engine IC. The following discussion explains these technologies in further detail, as well as our historical licensing activities, which we expect to continue to generate the majority of our revenues in 2012.

1T-SRAM

        Our innovative 1T-SRAM technologies provide major advantages over a traditional SRAM in cell stability, memory density and power consumption, making it more economical for designers to incorporate large amounts of embedded memory in their designs. In addition, our 1T-SRAM technologies offer all the benefits of the traditional SRAM, such as low latency, high-speed and the opportunity to use a simple interface. Our 1T-SRAM technologies can achieve these advantages while utilizing standard logic manufacturing processes and providing the simple, standard SRAM interface that designers are accustomed to.

High Density

        The high density of our 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, i.e., 6T-SRAM. Increased density enables manufacturers of electronic products, such as cellular phones, video game consoles and digital cameras and camcorders, to incorporate additional functionality into a single IC, generally an SoC, resulting in overall cost savings.

Low-power Consumption

        Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging.

7

Table of Contents

High-speed

        Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology.

SerDes (I/Os)

High-speed

        To meet increasing system performance requirements, which in many cases are being driven by the growth in the Internet and the need to transmit data faster, systems are requiring both more memory and faster communication between ICs in a system. Our interface technology includes high-speed serial I/Os, called SerDes. Our SerDes technology allows for fast exchange of data between ICs in the system and can support data rates of 2.5 to 11 Gbps in a number of protocols, including XAUI, 10G KR, and PCI Express (generations 1 to 3). We are developing next generation SerDes solutions, which we are targeting to achieve data rates of 15 Gbps and support advanced geometry nodes, such as 28 nanometers, primarily for use in our IC products.

Interoperability

        We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our licensees' ICs.

Low power

        While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os have higher power consumption, which is a challenge for IC designers. Our customers' SerDes I/O designs have stringent power consumption requirements, which represent a significant challenge for our engineering team. If the power consumption of the SerDes I/O is too high, the SoC must be redesigned as the power consumption budget for the SoC will be exceeded.

Our Strategy

        Our primary business objective is to become an IP-rich fabless semiconductor company offering serial chip-to-chip communication solutions that deliver unparalleled bandwidth performance for next generation networking systems. The key components of the expansion of our strategic plan to become an IC supplier include the following IC-focused strategies:

Target Large and Growing Markets

        Our initial strategy is to target the networking equipment market, which is a multi-billion dollar market led by companies such as Cisco Systems, Inc., Juniper Networks, Inc., Huawei Technologies, ZTE Corporation, Alcatel-Lucent and several others. To date, we have secured two low-volume design wins, which means the customer has completed its prototype evaluation and has informed us that its next generation systems will use our Bandwidth Engine IC. We are engaged with multiple customers, where we are working to achieve design wins.

8

Table of Contents

Leverage Technologies to Create New Products

        Our strategy is to combine our proprietary IP and design expertise to address the needs of several upcoming generations of advanced networking equipment. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost and using less power. We intend to develop a Bandwidth Engine product portfolio that can serve a wide range of system performance requirements and provide cost reduction options. In addition, we can provide customized IC solutions to customers using their proprietary technology and architecture, which would allow for improved communication between our Bandwidth Engine IC and the customer's packet processor.

        Another strategy is to leverage our high-speed serial I/O to create non-memory denominated ICs, which will work along side the Bandwidth Engine ICs on 100 Gbps and higher system solutions. This will provide our customers with a more complete solution, and possibly allow us to sell a chipset containing multiple MoSys ICs.

Build Long-Term Relationships with Suppliers of Packet Processors

        A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. To that end, we have been working closely with FPGA, ASIC and NPU providers, to demonstrate interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems. As we engage with application-specific standard product and NPU providers, we will be developing characterization kits to support their products as well. We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to speed our time-to-market, provide us with a competitive advantage and expand our target markets.

Expand Adoption of the GigaChip Interface Protocol

        Our goal is for GCI to become an open industry standard that is designed into other ICs in the system, as we believe this will further enable serial communication at the board level and encourage adoption of our Bandwidth Engine IC products. To this end, in July 2010, we launched the GigaChip Alliance, which we have been promoting to become a consortium of leading semiconductor and system companies collaborating with us to develop the industry-wide open interoperability standards and tools required to accelerate this advanced serial chip-to-chip interface. Currently, this consortium is comprised of an informal group of early adopters who have agreed to support the GCI by demonstrating interoperability of the Bandwidth Engine IC in their systems. Since 2010, we have publicly announced the following GCI supporters: Altera Corporation, Avago Technologies, Inc., LSI, Inc., NetLogic Microsystems, Inc. (recently acquired by Broadcom Corporation) and Xilinx, Inc. In addition, multiple network equipment companies, which are prospective customers, have adopted GCI.

Licensing and Distribution Strategy for our IP

        Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing

9

Table of Contents

relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, our IP licensing activities will be limited in 2012 and beyond. We intend to avoid future licensing projects that require significant use of our engineering resources, as the vast majority of our engineering personnel now work on the Bandwidth Engine ICs. However, during 2012, substantially all of our revenues will be generated from licensing and royalties related to our existing licensing arrangements, as we continue to perform and deliver under outstanding license agreements and collect royalties from 1T-SRAM licensees.

        Customers in the United States accounted for 39%, 38% and 24% of our revenues in 2011, 2010 and 2009, respectively. Customers in Japan accounted for 33%, 43% and 64% of our revenues in 2011, 2010 and 2009, respectively. Customers in Taiwan accounted for 23%, 18% and 11% of our revenues in 2011, 2010 and 2009, respectively. Our remaining revenues were from customers in the rest of Asia and in Europe.

Project Licenses

        Historically, we formed product development and IP licensing relationships directly with semiconductor companies. In these relationships, the prospective licensee's implementation of our technologies typically included customized development. Usually, these relationships involved both engineering work to implement our technology in the specified product and licensing the technology for manufacture and sale of the product. Although the precise terms contained in our license agreements vary, they generally include licensing fees, development fees for customizations based on the achievement of specified development milestones and royalties. The vast majority of our contracts allow for milestone billings based on work performed. If we perform the contracted services, usually the licensee is obligated to pay the license fees even if the licensee cancels the project prior to completion. The agreements often also provide for the payment of additional contract fees if we provide engineering or manufacturing support services related to the manufacture of the product. Provisions in our memory license agreements generally require the payment of royalties to us based on the future sale or manufacture of products utilizing our technologies. Generally, our project licenses grant rights on a non-exclusive, non-transferable basis, limited to the use of our technology as modified for the project covered by the license agreement. Our license agreements generally have a fixed term and are subject to renewal. Each new project requires a separate agreement or an addendum to modify an existing agreement. We are not expecting to enter into similar kinds of projects in the future, as such licenses generally require significant engineering effort and support.

Technology Licenses

        We also offer our technology to semiconductor companies and foundries through 1T-SRAM and I/O technology license agreements, under which we grant the licensee the additional right to create and modify designs to offer to its own customers or use internally. The contract fees associated with these arrangements typically require the licensee to pay us to port our technology to the licensee's manufacturing process and develop a template design that the licensee will be able to use to generate future designs. These agreements also may obligate the licensee to pay contract fees upon the achievement of specified development milestones and may provide for the payment of additional contract fees for engineering or manufacturing support services. Our memory technology license agreements include royalty provisions based on the sale or manufacture of products utilizing our technologies. The technology licenses are non-transferable and authorize the licensee to modify designs for its customers or internal use from the template design that we provide under the agreement. Typically, the template design applies only to a specified manufacturing process generation or specific application. The licensee may add future process generations or uses to the license agreement for additional contract fees.

10

Table of Contents

Research and Development

        Our ability to compete in the future depends on improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing even higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our Bandwidth Engine IC products requires the hiring of specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. Our significant future research and development activities will include:

•

designing next generation ICs with larger memory blocks and higher-speed SerDes;



•

developing versions of our initial Bandwidth Engine IC with alternative features, such as lower-speed SerDes or smaller memory blocks to allow us to serve a broader range of applications and systems;



•

porting our 1T-SRAM and SerDes technology to more advanced foundry process nodes; and



•

developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

        As of December 31, 2011, we employed 120 individuals in engineering and research and development, of which 43 were employed in our facility in Hyderabad, India. For the years ended December 31, 2011, 2010 and 2009, research and development expenditures totaled approximately $26.2 million, $25.5 million and $19.3 million, respectively.

Sales and Marketing

        As of December 31, 2011, we had 11 sales, marketing and application engineering personnel managing and supporting our IP licensing activities and securing design wins for our Bandwidth Engine product. Our application engineers actively engage with customers to introduce them to our Bandwidth Engine product capabilities and demonstrate its inter-operability within their systems. Our sales and marketing personnel are located in the United States, Japan and China. In addition to our direct sales team, we sell our technologies through sales representatives and distributors in the United States and Asia.

        Our IP revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2011, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, Renesas Electronics Corporation, or Renesas, and Broadcom represented 23%, 17% and 12% of total revenue, respectively. For the year ended December 31, 2010, Renesas, TSMC and Rohm Co., Ltd. represented 23%, 18% and 15% of total revenue, respectively. For the year ended December 31, 2009, Renesas, TSMC and Fujitsu Microelectronics, Ltd. represented 44%, 10% and 10% of total revenue, respectively.

Intellectual Property

        We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

        As of December 31, 2011, we held approximately 70 U.S. and 40 foreign patents on various aspects of our technology, with expiration dates ranging from 2012 to 2028. We currently have approximately 40 pending patent applications in the U.S. and abroad. There can be no assurance that others will not

11

Table of Contents

independently develop similar or competing technology or design around any patents that may be issued to us, or that we will be able to enforce our patents against infringement.

        In December 2011, we sold 43 U. S. and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which, at one time, was a principal focus of our historical 1T-SRAM licensing activities.

        The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

        The markets for our Bandwidth Engine IC products are highly competitive. We believe that the principal competitive factors are:

•

processing speed and performance;



•

density and cost;



•

low-power consumption;



•

reliability;



•

interface requirements;



•

ease with which technology can be customized for and incorporated into customers' products; and



•

level of technical support provided.

        We believe that we compete favorably with respect to each of these criteria. Using our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP provides our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc. and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Elpida Memory, Inc., Micron Technology and others. SRAM solutions can meet high-speed performance requirements, but the memory size is often inadequate. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation, GSI Technology, Inc. and Samsung Electronics Co., Ltd. The majority of the currently available SRAM and DRAM solutions use a parallel rather than a serial I/O. To offset these drawbacks, system designers use more discrete memory ICs, resulting in higher power consumption and

12

Table of Contents

greater utilization of space on the line card. Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than we are able to respond to new or emerging technologies or changes in customer requirements. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

        Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has almost no history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our new chip-to-chip communication protocol, GCI. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or if they believe it might complicate their development process or increase their cost. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier class and enterprise applications.

Manufacturing

        We depend on third-party vendors to manufacture, package, assemble and production test our Bandwidth Engine IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

        Manufacturing and Testing.     We use TSMC to manufacture and ASE, Inc. and Evans Analytical Group, LLC, to assemble, package and production test our IC products. We utilize eSilicon Corporation to manage and support our manufacturing and testing operations.

        Quality Assurance.     We maintain an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance exceeds the design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

Employees

        As of December 31, 2011, we had 143 employees, consisting of 120 in research and development and engineering, 11 in sales, marketing and application engineering and 12 in finance and administration. By location, we had 97 employees in the United States, 43 in our development center in India and 3 sales and marketing employees in Asia. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

Available Information

        We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on

13

Table of Contents

Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and copy any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

        Leonard Perham,     Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors of MoSys and served on our Board of Directors from 1991 to 1997. Since 2000, Mr. Perham retired from Integrated Device Technology, Inc., or IDT, where he served as its Chief Executive Officer from 1991 and President and board member from 1986. From March 2000 to February 2012, Mr. Perham served as a member of or chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company. Mr. Perham also has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog, Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

        James W. Sullivan,     Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

        Thomas Riordan,     Mr. Riordan became our Chief Operating Officer and Executive Vice President in May 2011. Prior to joining the Company, Mr. Riordan was President and Chief Executive Officer of Exclara, a fabless semiconductor supplier of ICs for solid-state lighting from 2006 until 2010. From 2000 to 2004, Mr. Riordan served as Vice President of PMC-Sierra's microprocessor division. Mr. Riordan joined PMC-Sierra in August 2000 when it purchased Quantum Effects Devices, which he had co-founded and served as President and Chief Executive Officer. Mr. Riordan serves on the board of directors of Mellanox Technologies and PLX Technology. Mr. Riordan holds Bachelor of Science and Master of Science degrees in Electrical Engineering as well as a Bachelor of Arts degree in Government from the University of Central Florida and has done post-graduate work in Electrical Engineering at Stanford University.

14

Table of Contents

        David DeMaria,     Mr. DeMaria became our Vice President of Business Operations in August 2008. From November 2007 until August 2008, Mr. DeMaria served as Senior Vice President at Apache Design Solutions, an electronic design automation software company. From January 2006 until November 2007, Mr. DeMaria was Chief Executive Officer of Optimal Corporation, an electronic design automation software company that he helped grow and ultimately merge with Apache Design Solutions. From October 1999 to March 2004, Mr. DeMaria served in various positions, including Executive Vice President of the systems business unit and Senior Vice President of worldwide marketing and strategy, at Cadence Design Systems. Mr. DeMaria attended Boston University for a Bachelor of Science degree in Computer Engineering.